The invention relates generally to priority interrupt control circuits; and specifically, the invention provides a circuit for handling a number of randomly occurring interrupt signals and providing these signals to a central processing unit on the basis of their priority.
Every computer system requires that the processing unit respond to a number of different conditions and devices on a random basis. Such devices include peripheral devices operating in conjunction with the processing unit, and such conditions include power failure, start-up procedures, programming errors, and other fault conditions which may occur. These conditions and devices request the attention of the processing unit by generating interrupt signals. The interrupt signals may be recognized in many ways, e.g., first-come first-served basis, a first-come first-ready first-served basis, a straight priority basis, etc. The disclosed apparatus is applicable to a straight priority system. In this case, each interrupt signal is assigned a priority as a function of its importance relative to the other interrupt signals. The apparatus is operative to receive the interrupt signals, separate them on the basis of priority, and transmit them to the processing unit in order of descending priority.
There is substantial prior art in the area of priority interrupt control systems. Further, the philosophy of handling priority interrupts varies from a fixed priority system which operates on the basis of transmitting the highest priority interrupt signal first to a system in which the priority structure is controlled by an algorithm in the system.
The present disclosure is oriented to a system in which the interrupt signals are handled by apparatus separate from the processing unit and in which the interrupt signals are transferred to the processing unit solely on the basis of priority.
In a typical prior art system, each interrupt signal has its own interrupt circuit. The circuit contains a number of storage elements; and the circuits are chained together in a series circuit in which each circuit is dominant over circuits below it in the chain and subordinate to the circuits above it in the chain. Such an interrupt structure requires great duplicity in the circuit elements.
The disclosed apparatus provides an interrupt structure in which the number of duplicate circuits is greatly reduced thereby providing a substantial economy in the interrupt structure design.